This invention relates in general to masking techniques, including photoresist masking techniques, for the etching of silicon.
In particular, the invention relates to a process for decreasing mask degradation, and for increasing the silicon:mask etch selectivity ratio in-situ during the silicon etch process and to the protective cap formed on the mask as the result.
As measured by the minimum feature size and device density, the scale of integration of semiconductor devices on integrated circuit chips (IC) has been improved greatly since the middle and late 1970's. In fact, over the past five years, the silicon IC technology has grown from large scale integration (LSI) to very large scale integration (VLSI), and is projected to grow to ultra-large scale integration (ULSI) by the end of the decade of the 1980's. This continued improvement in silicon integrated circuit integration has been made possible by advances in integrated circuit manufacturing equipment, as well as in the materials and methods used in processing semiconductor wafers into IC chips. Some of the most dramatic advances in manufacturing equipment have involved improved apparatus for lithography and etching. Generally, the density of integrated circuits and their speed of operation are dependent upon the accuracy and resolution of the lithography and etching apparatus which is used to form patterns of circuit elements in masking layers on the semiconductor wafer and then precisely replicate those patterns from the masking layers in the underlying semiconductor wafer layer(s).
FIG. 1 shows a widely used, low pressure ion-assisted plasma etching reactor system 10 which is available from Applied Materials, Inc. of Santa Clara, Calif. as the 8100 series etching system. The particular series is widely used within the industry for etching dielectrics such as oxides, nitrides and organic materials, for polysilicon and single crystal silicon etching, and for the etching of aluminum and aluminum alloys, all with a high degree of anisotropy.
The ion-assisted plasma etching reactor system 10 utilizes a process chamber having a metal wall 11 which serves as the anode in the RF system. Gas from a module 12 enters the chamber via gas inlet 13 and gas distribution ring or manifold 14 located at the top of the chamber. Spent etch products and gases are exhausted via ports 15 and 16. The exhaust port 15 is connected to a variable throttle valve 17 which, in response to the pressure sensing by a capacitive manometer 18, controls the chamber pressure by varying the pumping speed according to process requirements. The system exhaust port 15 is connected via the variable throttle valve 17 to a turbo molecular pump 19 which provides process pressures of about 3 to 300 millitorr and to a mechanical roughing pump 20. A nitrogen purge line is also provided for backfilling the process chamber with nitrogen to atmospheric pressure at the end of the etching process cycle. Exhaust port 16 is connected to a high speed cryo pump 22. The cryo pump 22 is used to provide very rapid pump-down of the process chamber to a low base pressure in addition to removal of water vapor from the chamber and residual water vapor absorbed in photoresist. The wafers 23 are vertically mounted on trays which are mounted on a rotatable hexagonal electrode or hexode 24 within the 24-inch diameter bell jar process chamber. The system is asymmetrical in the sense that the area of the cathode or hexode 23 is small in relation to the area of the bell jar wall or anode 11. This feature, in combination with low pressure operation, provides controlled bombardment to achieve the desired anisotropic etch reactions. RF power is supplied via a 13.56 MHz generator 25 which is coupled by a RF matching network 26 to the process chamber electrodes.
The ion-assisted plasma etch reactor system 10 shown in FIG. 1 has become a workhorse in the semiconductor industry since its introduction only a few years ago. In this system, the asymmetrical electrode arrangement and low pressure operation provide a controlled anisotropic etch reaction, characterized by excellent line width and etch rate uniformities for within-a-wafer, wafer-to-wafer and run-to-run measurements. The low pressure and controlled gas chemistry and process chamber temperatures provide clean etching surfaces and a clean system. In addition, the combination of low pressure operation at low power density levels provides excellent high selectivity to base layers. The system also is capable of sequential etching of different layers.
Despite the above-mentioned improvements made in the lithography and etching technologies over the last several years and despite the existence of excellent reactors, such as the system 10, FIG. 1, which are capable of reproducible, anisotropic etch performance, the current and future advanced bipolar, NMOS and CMOS technologies increasingly strain the capabilities of the existing mask technologies. In order to provide the very small minimum feature size IC chips used in these advanced technologies, it is necessary to prevent degradation or etching of the mask during the etch process and to very precisely maintain both the thickness and the lateral dimensions of the mask, both to provide exact replication of the mask in the etched layer such as polysilicon and to prevent phenomena such as punch-through in reduced thickness mask regions over stepped IC topographies. The result is the requirement of a very high layer-to-mask etch selectivity. Unfortunately, the resist masks which are used to pattern silicon provide silicon:mask etch selectivities of only about (1-2):1 using standard RIE (reactive ion etching) techniques. Higher selectivities are possible, for example, by incorporating appropriate species in the plasma etching gas to form an etch-protective polymer on the sidewalls of the silicon, but this is done at the expense of a relatively dirty process and of removing the polymer.
Accordingly, it is a principal object of the present invention to provide a process which forms a protective etch-resistant cap over the etch mask in-situ, as part of a standard plasma etch sequence.
It is another object of the present invention to provide an in-situ pre-etching procedure for forming a protective cap on an etch mask, which provides very high layer:mask etch selectivity.
It is also an object of the present invention to provide an in-situ pre-etching procedure for forming a protective etch-impervious cap on resist masks which provides very high silicon:mask etch selectivity and is readily removed when the mask is removed.
In one aspect, the present invention relates to a process for forming an etch-impervious layer on a mask over a layer in-situ preparatory to the etching of the layer, by exposing the mask to a plasma etching gas to form an oxidizable coating on the mask, and exposing the coating to an oxidizing gas plasma containing an etching species to oxidize the coating without substantial oxidation of the layer which is to be etched.
In another aspect, the present invention relates to a process for preparing an etch-impervious layer on a mask over a silicon-containing layer in-situ preparatory to etching the silicon-containing layer, by exposing the mask to a chlorine-containing etching gas plasma to form an oxidizable silicon-chlorine containing coating on the mask, and exposing the mask to an oxidizing plasma-containing oxygen or an oxygen-containing species and a chlorine-containing silicon etching species to oxidize the coating without oxidizing the silicon-containing layer.
The resulting cap is essentially impervious to etchant species such as chlorine so that, after the cap formation, the resist is protected from attack by the plasma etch process used to pattern the underlying layer.
As a consequence, after the cap is formed, the layer:mask etch selectivity is very high and is essentially independent of the length of the etch process and accompanying overetch, even for long etch and overetch times. In addition, the cap is easily removed as part of the standard mask removal process.
In another aspect, the cap could be formed on a non-silicon-containing layer by applying a silicon-containing gas such as carbon tetrachloride to the process gas flow which is used to form the cap coating.